The ever increasing degree of size reduction and integration in semiconductor devices has posed a serious problem with delay in electric signals resulting from the time constant of interconnections. A solution to this problem is the replacement of aluminum (Al) alloy by copper (Cu) having a lower electric resistance for conductive layers in multilayer interconnection.
Unlike Al, which is a conventional metallic material used for multilayer interconnections, Cu presents difficulties in patterning by dry etching. Consequently, Cu multilayer interconnections are usually obtained by the damascene technique which consists of forming trenches in the insulating film and filling them up with Cu, thereby forming a wiring pattern. It has developed into the dual damascene technique, as disclosed in Japanese Patent Application No. Hei 10-143914, which consists of forming via holes and wiring trenches and filling them up with Cu at the same time. It is attracting attention because it reduces the number of processing steps.
Meanwhile, high-integration semiconductor devices, whose speed decreases as the wiring capacity increases, definitely needs fine multilayer interconnections with low dielectric constant interlayer insulating film for reduction in wiring capacity.
Raw materials for the low dielectric constant interlayer insulating film include fluorine-containing silicon oxide (FSG), having ∈≈3.5, which has been in practical use, as well as organosilicon polymer, such as polyaryl ether (APE), and inorganic materials, such as hydrogensilsesquioxane (HSQ) and methylsilsesquioxane (MSQ), having ∈≈2.7. Recently, rendering them porous is being attempted to further reduce their dielectric constant to about 2.2.
For the dual damascene technique to be successfully applied to the low dielectric constant interlayer insulating film, it is necessary to overcome the following technical limitations.
(1) The low dielectric constant film is similar in composition to the resist used for patterning; consequently, it is readily damaged while the resist is being removed. In other words, the low dielectric constant film should be protected from damage that might occur when the resist mask is peeled off after etching or when patterning is repeated because of failure to meet product specifications.
(2) The low dielectric constant film should be applicable to the borderless structure in which there is no margin for alignment of wirings with via holes.
With size reduction of semiconductor devices in the latest generation to realize the design rule of 0.18 μm, it is essential for multilayer interconnections to be fabricated by a process applicable to the borderless structure. This process should be able to minimize the variation of via hole resistance due to misalignment even in the case where wiring trenches and via holes are formed at the same time by the dual damascene technique in the interlayer dielectric including the low dielectric constant film.
(3) For the wiring trenches to be formed with a well-controlled depth, it is desirable to place an etch stopping film near the bottom of the wiring trench. Unfortunately, an etch stopping film with a comparatively high dielectric constant increases the interlayer capacity if it exists in the interlayer dielectric.
Consequently, there is a demand for the dual damascene technique for the low dielectric constant film which forms the wiring trenches without increase in capacity.
The dual damascene technique which overcomes the above-mentioned technical limitations has been disclosed in Japanese Patent Laid-open Nos. 2000-150519 and 2001-44189.
A description is given below with reference to FIGS. 5A to 5G of the dual damascene technique for the low dielectric constant interlayer film which has been disclosed in Japanese Patent Laid-open No. 2001-44189. FIGS. 5A to 5G are sectional views showing the steps for forming the dual damascene structure according to the conventional process.
As shown in FIG. 5A, an underlying insulating film 1 is deposited on a substrate (not shown). On the underlying insulating film 1 is formed an interlayer insulating film, which is a laminate film consisting of an organic film 2 and a silicon oxide (SiO2) film 3. In the interlayer insulating film is formed buried wiring 4 of copper (Cu) film.
On the buried wiring 4 of Cu film are sequentially formed a silicon carbide (SiC) film 5, which is an anti-oxidizing film for the Cu film, a carbon-containing silicon oxide (SiOC) film 6, which is a methylsilsesquioxane (MSQ) film, and a polyaryl ether (PAE) film 7, which is an organic film.
Further, a silicon oxide (SiO2) film 8, as a first mask forming layer, and a silicon nitride (SiN) film 9, as a second mask forming layer, are sequentially formed. On the SiN film 9 is formed a resist mask 10 with a pattern of wiring trenches.
As shown in FIG. 5B, the SiN film 9 undergoes dry etching through the resist mask 10, so that a second mask 11 of SiN film is formed, which has the pattern of wiring trenches. Then, the resist mask 10 is removed.
A resist mask 12 having the pattern of via holes is formed on the second mask 11 and the SiO2 film 8, in such a way that the resist pattern of via holes overlaps at least partly with the second mask 11 of SiN film having the pattern of wiring trenches.
As shown in FIG. 5C, the SiN film as the second mask 11 and the SiO2 film 8 as the first mask-forming layer undergo dry etching through the resist mask 12 having the pattern of via hole, so that openings are made. Then, the PAE film 7 undergoes etching to form via holes 13 through which the SiOC film 6 is exposed. The resist mask 12 may be removed at the same time as the PAE film 7 is removed by etching.
While openings are being made in the PAE film 7, the resist mask 12 becomes thinner; however, it is still possible to make the via holes 13 in good shape because there remains the first mask 8A of SiO2 film which functions as a mask.
As shown in FIG. 5D, the SiO2 film 6 undergoes etching, so that the via hole 13 is dug down to the SiC film 5 and the via hole 14 is formed. When the via hole 14 has been formed, the SiO2 film 8 constituting the first mask 8A remains in the region where the wiring trench is formed. This SiO2 film 8 is removed at the same time as etching that uses as a mask the second mask 11 of SiN film having the pattern of wiring trenches. Thus, the opening 15 is formed.
As shown in FIG. 5E, the PAE film 7 remaining on the bottom of the opening 15 undergoes etching, so that the wiring trench 16 is formed. The SiC film 5 remaining on the bottom of the via hole 14 undergoes etching, so that the via hole 14 communicates with the buried wiring 4 of Cu. In this way the wiring trench 16 and the via hole 14 are formed or the processing for dual damascene is completed.
Incidentally, the second mask 11 of SiN film remaining outside the region where the wiring trench is formed is removed when etching is performed on the SiC film 5 remaining on the bottom of the via hole 14.
Next, post treatment with a chemical solution and RF sputtering are carried out to remove etching residues sticking to the side walls of the wiring hole 16 and the via hole 14, and the deteriorated Cu layer in the bottom of the via hole 14 is restored. Then, as shown in FIG. 5F, a Ta film 17 as barrier metal is formed by sputtering. A. Cu film 18 is deposited by electrolytic plating or sputtering, so that the wiring trench 16 and the via hole 14 are filled up.
As shown in FIG. 5G, the Ta film 17 and Cu film 18 which have been deposited undergo chemical-mechanical polishing (CMP) so that those parts unnecessary for the wiring pattern are removed. In this way there is obtained the multilayer interconnections of dual damascene structure.
Further, the dual damascene wiring 18 is covered with the SiC film 19 as an anti-oxidizing layer, as in the case of the filled Cu wiring 4 in the lower layer.
The dual damascene technique that employs the double-layer etching mask mentioned above overcomes the above-mentioned technical limitations involved in the low dielectric constant interlayer film.
In other words, even if the resist masks 10 and 12 do not meet the product specifications, their reprocessing can be accomplished on the first mask forming layer 9 or the second mask forming layer 8 and the removal of the resist mask 12 to form the via hole can be accomplished at the same time as the PAE film 7 is etched to form the via hole 13. This makes it possible to peel off the resist while protecting the low dielectric constant film from damage.
Since the via hole 13 (or 14) is made through the second mask 11, which is an SiN film having the wiring pattern, the via hole 14 remains unchanged in dimensions even if there is a misalignment of the wiring trench 16 with the via hole 14.
Moreover, when the wiring trench 16 is formed in the PAE film 7 which has been formed on the SiOC film 6, it is possible to etch them with a desired etching ratio, because the SiOC film 6 is an inorganic MSQ film and the PAE film 7 is an organic polymer film. This makes it possible to easily control the depth of the wiring trench 16 without requiring the etch stopping film, which is an SiN film or the like having a high dielectric constant.
Notwithstanding, the conventional dual damascene technique mentioned above still has the following problems if it is to be applied to the multilayer interconnections according to the latest design rule smaller than 0.1 μm.
The first problem is that the second mask forming layer or the SiN film 9 tends to become thick. The second mask 11 should have a certain thickness because it is used when the via hole 14 is formed by etching the SiOC film (MSQ film) of the via hole interlayer film and the opening 15 is formed in the region where the wiring trench is formed. For example, in the case where the second mask 11 is the SiN film 9 and opening is made in the SiOC film 6 (400 nm thick) which is the via hole interlayer film, the SiN film 9 should have a thickness of 100 to 150 nm in view of the etching selective ratio so that the wiring trench will not widen upward or will not have a round shoulder. The thickening of the second mask forming layer poses the second problem as follows.
The second problem is that the resist mask 12 is often formed on steps and this makes it difficult to accurately form fine patterns.
As shown in FIG. 5B, the SiN film 9 which is the second mask forming layer is etched to form the second mask 11 which has the wiring trench pattern. In this step, the etching selective ratio (SiN/SiO2) is from 2 to 3 at the highest for the SiO2 film 8, which is the first mask forming layer. Therefore, when the SiN film 9 undergoes overetching, the underlying SiO2 film 8 is usually eroded by about 30 nm. Thus, the resist mask 12 which has the via hole pattern has to be formed on a step which is 130 to 180 nm high.
Forming a fine resist pattern conforming to the design rule of 0.10 μm on a step slightly lower than 200 nm is much harder than forming on a flat part because it presents difficulties in line width control and it gives slant pattern bottoms.
The third problem is associated with the coat-type anti-reflection coating (BARC) generally used in lithography. The BARC varies in shape depending on the pattern dimensions and density of the second mask 11 to which it is applied. This leads to variation in depth of focus, which in turn aggravates the shape of resist at the time of exposure and also aggravates the shape of the second mask 11 when the BARC is etched to form the via hole.
The fourth problem is associated with misalignment of the upper layer wiring with the via hole. According to the conventional dual-damascene technique mentioned above, the wiring trench is formed by patterning through the resist mask 10 and then the via hole 13 is formed by patterning through the resist mask 12. Therefore, the mask for the wiring trench 16 is aligned indirectly with the mask for the via hole 14, and alignment in this manner results in a larger displacement of the upper layer wiring from the via hole than the conventional process in which the pattern for the via hole is formed previously.
One way to tackle these problems, which is disclosed in Japanese Patent Laid-open No. 2000-150519, is to form the second mask from a metal film, thereby raising the etch selecting ratio for the MSQ film (the via hole interlayer film), so as to make the second mask thin and reduce the height of steps in the resist.
Unfortunately, a metal film is almost opaque to light of ordinary wavelengths (200 to 1000 nm) used for mask alignment. Therefore, overall coating with a metal film disables alignment by light of ordinary wavelengths or alignment by image processing.
Now, it is an object of the present invention to provide an efficient and high-yield production method of a highly reliable semiconductor device having multilayer interconnections, the method being characterized in forming the dual damascene structure in the low dielectric constant interlayer insulating film composed of PAE film and MSQ film in such a way as to reduce load on resist patterning, thereby giving the dual damascene structure in proper form.